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PRELIMINARY TECHNICAL DATA
a
1MSPS, 12- / 10-/ 8-Bit ADCs in 6 Lead SC70 Preliminary Technical Data AD7476A/AD7477A/AD7478A
FUNCTIONAL BLOCK DIAGRAM
V DD
FEATURES Fast Throughput Rate: 1MSPS Specified for VDD of 2.35 V to 5.25 V Low Power: 3 mW typ at 1MSPS with 3V Supplies 12.5mW typ at 1MSPS with 5V Supplies Wide Input Bandwidth: 70dB SNR at 100kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface SPITM/QSPITM/MICROWIRETM/DSP Compatible Standby Mode: 1A max 6-Lead SC70 Package APPLICATIONS Battery-Powered Systems Personal Digital Assistants Medical Instruments Mobile Communications Instrumentation and Control Systems Data Acquisition Systems High-Speed Modems Optical Sensors
V IN
T/H
8-/10-/12-BIT SUCCESSIVE APPROXIMATION ADC
SCLK
CONTROL LOGIC
SDATA
&6
AD7476A/AD7477A/AD7478A GND
The reference for the part is taken internally from VDD. This allows the widest dynamic input range to the ADC. Thus the analog input range for the part is 0 to VDD. The conversion rate is determined by the SCLK. PRODUCT HIGHLIGHTS 1. First 8-/10-/12-Bit ADCs in a SC70 package. 2. High Throughput with Low Power Consumption. 3. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power consumption to be reduced when a power-down mode is used while not converting. The part also features a Power Down mode to maximize power efficiency at lower throughput rates. Current consumption is 1A max when in Power Down mode. 4. Reference derived from the power supply. 5. No Pipeline Delay. The parts feature a standard successive-approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control.
GENERAL DESCRIPTION The AD7476A/AD7477A/AD7478A are 12-bit, 10-bit and 8-bit, high speed, low power, successive-approximation ADCs respectively. The parts operate from a single 2.35 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. The parts contain a low-noise, wide bandwidth track/hold amplifier which can handle input frequencies in excess of 6MHz. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. There are no pipelined delays associated with the part. The AD7476A/AD7477A/AD7478A use advanced design techniques to achieve very low power dissipation at high throughput rates.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.
REV. PrE (03/02)
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
+5.25 V, f =20 MHz, AD7476A-SPECIFICATIONS1 T(V=T=+2.35T V tounless otherwise noted.)f to ,
DD SCLK A SAMPLE=1
MSPS unless otherwise noted;
Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 3 Signal-to-Noise Ratio (SNR) 3 Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Intermodulation Distortion (IMD) 3 Second Order Terms Third Order Term Aperture Delay Aperture Jitter Full Power Bandwidth Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity 3 Differential Nonlinearity
A Grade
MIN 1,2
MAX
B Grade1,2 Units
Test Conditions/Comments fIN = 100 kHz Sine Wave
70 69 71 70 -82 -84 -84 -84 10 30 6.5 TBD
70 69 71 70 -82 -84 -84 -84 10 30 6.5 TBD
dB dB dB dB dB dB
min min min min typ typ
VDD= VDD= VDD= VDD=
2.35V 4.75V 2.35V 4.75V
to to to to
3.6V 5.25V 3.6V 5.25V
dB typ dB typ ns max ps typ MHz typ MHz typ
fa= 100.73 kHz, fb= 90.72 kHz fa= 100.73 kHz, fb= 90.72 kHz
@ 3 dB @ 0.1dB
12 0.75
12 1 0.9
0.9 Offset Error3 1.5 Gain Error 3 1.5 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN,SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN5 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance5 Output Coding CONVERSION RATE Conversion Time Track/Hold Acquisition Time 3 Throughput Rate 1.5 1.5
B Grade, See Note 4 Bits LSB max LSB typ LSB max Guaranteed No Missed Codes to 12 Bits LSB typ LSB max LSB typ LSB max LSB typ
0 to VDD 0 to VDD Volts 1 1 A max 30 30 pF typ 2.4 1.8 0.8 0.4 1 1 10 2.4 1.8 0.8 0.4 1 1 10 V min V min V max V max A max A typ pF max
V DD = 2.35V VDD= 3.6 to 5.25V VDD= 2.35 to 3.6V Typically 10 nA, VIN= 0 V or VDD
VDD - 0.2 VDD - 0.2 V min 0.4 0.4 V max 10 10 A max 10 10 pF max Straight (Natural) Binary 800 400 200 1 2.35/5.25 2.5 1.25 3.5 1.8 800 400 200 1 ns max ns max ns max MSPS max
ISOURCE= 200 A;VDD= 2.35 V to 5.25 V I SINK =200 A
16 SCLK Cycles Full-scale step input Sine wave input <= 100 KHz See Serial Interface Section
POWER REQUIREMENTS VDD I DD Normal Mode (Static) Normal Mode (Operational)
2.35/5.25 V min/max 2.5 1.25 3.5 1.8 mA mA mA mA typ typ max max Digital I/Ps= VDD= 4.75V VDD= 2.35V V DD= 4.75V V DD= 2.35V 0V or VDD. to 5.25V,SCLK On or Off. to 3.6V,SCLK On or Off. to 5.25V, fSAMPLE=1MSPS to 3.6V, f SAMPLE=1MSPS
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PRELIMINARY TECHNICAL DATA
AD7476A-SPECIFICATIONS1
Parameter POWER REQUIREMENTS (continued) Full Power-Down Mode Power Dissipation 6 Normal Mode (Operational) Full Power-Down 1
(VDD=+2.35 V to +5.25 V, fSCLK=20 MHz, fSAMPLE=1 MSPS unless otherwise noted; TA=TMIN to TMAX, unless otherwise noted.)
Units Test Conditions/Comments
A Grade1,2 B Grade1,2
1
A max
17.5 5.4 5 3
17.5 5.4 5 3
mW max mW max W max W max
V DD = V DD = VDD= VDD=
5V, fSAMPLE= 1MSPS 3V, fSAMPLE= 1MSPS 5V 3V
NOTES 1 Temperature ranges from -40C to +85C. 2 Operational from V DD = 2.0V, with input low voltage (V INL ) 0.35V max. 3 See Terminology. 4 B Grade, maximum specs apply as typical figures when V DD = 4.75V to 5.25V. 5 Sample tested @ +25C to ensure compliance. 6 See Power Versus Throughput Rate section. Specifications subject to change without notice.
+5.25 V, f =20 MHz, AD7477A-SPECIFICATIONS1 (V=T=+2.35T V tounless otherwise noted.)f T to ,
DD SCLK A MIN MAX
SAMPLE=1
MSPS unless otherwise noted;
Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 3 Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Intermodulation Distortion (IMD) 3 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN4
A Grade1,2 61 -73 -74 -78 -78 10 30 6.5 TBD 10 1 0.9 1 1 0 to VDD 1 30 2.4 0.8 0.4 1 1 10
Units dB min dB max dB max dB typ dB typ ns max ps typ MHz typ MHz typ Bits LSB LSB LSB LSB
Test Conditions/Comments fIN = 100 kHz Sine Wave
fa= 103.5 kHz, fb= 113.5 kHz fa= 103.5 kHz, fb= 113.5 kHz
@ 3 dB @ 0.1dB
max max max max
Guaranteed No Missed Codes to 10 Bits.
Volts A max pF typ V min V max V max A max A typ pF max
V DD = 5V V DD = 3V Typically 10 nA, VIN= 0 V or VDD
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PRELIMINARY TECHNICAL DATA
+5.25 V, f =20 MHz, AD7477A-SPECIFICATIONS1 T(V=T=+2.35T V tounless otherwise noted.)f to ,
DD SCLK A SAMPLE=1
MSPS unless otherwise noted;
Parameter LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance4 Output Coding CONVERSION RATE Conversion Time Track/Hold Acquisition Time 3 Throughput Rate POWER REQUIREMENTS VDD I DD Normal Mode(Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation 5 Normal Mode (Operational) Full Power-Down
A Grade
MIN 1,2
MAX
Units
Test Conditions/Comments ISOURCE= 200 A,VDD= 2.35 V to 5.25 V I SINK= 200A
VDD - 0.2 V min 0.4 V max 10 A max 10 pF max Straight (Natural) Binary 700 TBD 1 2.35/5.25 2 1 3.5 1.6 1 ns max ns max MSPS max V min/max mA typ mA typ mA max mA max A max
14 SCLK cycles with SCLK at 20 MHz
Digital I/Ps = 0V or VDD VDD= 4.75V to 5.25V, SCLK On or Off. VDD= 2.35V to 3.6V, SCLK On or Off. VDD= 4.75V to 5.25V, fSAMPLE = 1MSPS VDD= 2.35V to 3.6V, fSAMPLE = 1MSPS
17.5 4.8 5
mW max mW max W max
V DD= 5V, f SAMPLE = 1MSPS V DD= 3V, f SAMPLE = 1MSPS VDD= 5 V
NOTES 1 Temperature ranges from -40C to +85C. 2 Operational from V DD = 2.0V, with input high voltage (V INH)1.8 V min. 3 See Terminology. 4 Sample tested @ +25C to ensure compliance. 5 See Power Versus Throughput Rate section. Specifications subject to change without notice.
AD7478A-SPECIFICATIONS1 T = T
Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD)3 Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Intermodulation Distortion (IMD)3 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity 3 Differential Nonlinearity 3 Offset Error 3 Gain Error3 Total Unadjusted Error (TUE)3 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance 49 -65 -65
(VDD= +2.35 V to +5.25 V, fSCLK= 20MHz, fSAMPLE=1 MSPS unless otherwise noted; A MIN to TMAX, unless otherwise noted.)
Units dB min dB max dB max dB typ dB typ ns max ps typ MHz typ MHz typ Bits LSB max LSB max LSB max LSB max LSB max Volts A max pF typ REV. PrE fa= 498.7kHz, fb= 508.7kHz fa= 498.7kHz, fb= 508.7kHz Test Conditions/Comments fIN= 100 kHz Sine Wave
A Grade1,2
-68 -68 10 30 6.5 TBD 8 0.5 0.5 0.5 0.5 0.5 0 to VDD 1 30 -4-
@ 3 dB @ 0.1dB
Guaranteed No Missed Codes to 8 Bits.
PRELIMINARY TECHNICAL DATA
AD7478A-SPECIFICATIONS1
Parameter LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance4 Output Coding CONVERSION RATE Conversion Time Track/Hold Acquisition Time3 Throughput Rate POWER REQUIREMENTS VDD I DD Normal Mode(Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation 5 Normal Mode (Operational) Full Power-Down 2.4 0.8 0.4 1 1 10
(VDD=+2.35 V to +5.25 V, fSCLK=20 MHz, fSAMPLE=1 MSPS unless otherwise noted; TA=TMIN to TMAX, unless otherwise noted.)
Units V min V max V max A max A typ pF max Test Conditions/Comments
A Grade1,2
V DD = 5V V DD = 3V Typically 10 nA, VIN= 0 V or VDD
VDD - 0.2 V min 0.4 V max 10 A max 10 pF max Straight (Natural) Binary 600 TBD 1 2.35/5.25 2 1 3.5 1.6 1 ns max ns max MSPS max Vmin/max mA typ mA typ mA max mA max A max
ISOURCE= 200 A,VDD= 2.35 V to 5.25 V I SINK= 200A
12 SCLK Cycles with SCLK at 20 MHz
Digital I/Ps= 0V or VDD. VDD= 4.75V to 5.25V, SCLK On or Off. VDD= 2.35V to 3.6V, SCLK On or Off. VDD= 4.75V to 5.25V VDD= 2.35V to 3.6V
17.5 4.8 5
mW max mW max W max
V DD = 5V V DD = 3V VDD= 5 V
NOTES 1 Temperature ranges from -40C to +85C. 2 Operational from V DD = 2.0V, with input high voltage (V INH )1.8 V min. 3 See Terminology. 4 Sample tested @ +25C to ensure compliance. 5 See Power Versus Throughput Rate section. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA AD7476A/AD7477A/AD7478A TIMING SPECIFICATIONS1
Parameter fSCLK
2
(VDD= +2.35 V to +5.25 V; TA= TMIN to TMAX, unless otherwise noted.)
Units KHz min KMHz max AD7476A AD7477A AD7478A ns min ns ns ns ns ns ns ns ns ns s min min max max min min min min max typ Minimum Quiet Time required between Bus Relinquish and start of Next Conversion Minimum CS Pulse Width CS to SCLK Setup Time Delay from CS Until SDATA Three-State Disabled Data Access Time After SCLK Falling Edge. SCLK Low Pulse Width SCLK High Pulse Width SCLK to Data Valid Hold Time SCLK Falling Edge to SDATA High Impedance SCLK Falling Edge to SDATA High Impedance Power Up Time from Full Power-down. Description
Limit at TMIN, TMAX AD7476A/AD7477A/AD7478A 10 20 16 x tSCLK 14 x tSCLK 12 x tSCLK 50 10 10 20 20 0.4t SCLK 0.4t SCLK 10 10 25 1
t CONVERT
t QUIET t1 t2 t33 t43 t5 t6 t7 t84 t power-up 5
NOTES 1 Sample tested at +25C to ensure compliance. All input signals are specified with tr=tf=5ns (10% to 90% of VDD) and timed from a voltage level of 1.6 Volts. 2 Mark/Space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.0 V. 4 t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 5 See Power-up Time section. Specifications subject to change without notice.
t1
&6
tconvert t2
SCLK 1 2 3 4
t6
5 13
B
14 15 16
t5 t3
SDATA 3-STATE Z
t4
ZERO ZERO ZERO DB11 4 LEADING ZERO'S
t7
DB10 DB2 DB1
t8
DB0 3-STATE
tquie
t
Figure 1. AD7476A Serial Interface Timing Diagram
Timing Example 1 Having fSCLK = 20 MHz and a throughput of 1 MSPS, gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 1 s. With t2 = 10 ns min, this leaves tACQ to be 365 ns. This 365 ns satisfies the requirement of 200 ns for tACQ. From Figure 2, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 25 ns max. This allows a value of 215 ns for tQUIET satisfying the minimum requirement of 50 ns. Timing Example 2 Having fSCLK = 5 MHz and a throughput of 315 KSPS, gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 3.174 s.
With t2 = 10 ns min, this leaves tACQ to be 664 ns. This 664 ns satisfies the requirement of 200 ns for tACQ. From Figure 2, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, t8 = 25 ns max. This allows a values of 139 ns for tQUIET satisfying the minimum requirement of 50 ns. As in this example and with other slower clock values, the signal may already be acquired before the conversion is complete, but it is still necessary to leave 50 ns minimum tQUIET between conversions. In Example 2 the signal should be fully acquired at approximately point C in Figure 2.
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PRELIMINARY TECHNICAL DATA AD7476A/AD7477A/AD7478A
&6
tCONVERT t2
SCLK 1 2 3 4 5 13
B
14
C
15 16
t8
tQUIET
12.5(1/fSCLK)
tACQUISITION
1/THROUGHPUT
Figure 2. Serial Interface Timing Example
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise noted)
V DD to GND............................................-0.3 V to 7 V Analog Input Voltage to GND......-0.3 V to VDD + 0.3 V Digital Input Voltage to GND....................-0.3 V to 7 V Digital Output Voltage to GND....-0.3 V to VDD + 0.3 V Input Current to Any Pin Except Supplies2..........10 mA Operating Temperature Range Commercial (A, B Grade)..................-40C to +85C Storage Temperature Range..............-65C to +150C Junction Temperature..........................................150C SC70 Package JA Thermal Impedance....................................332C/W JC Thermal Impedance..................................120C/W Lead Temperature, Soldering Vapor Phase (60 secs)................................. +215C Infrared (15 secs)....................................... +220C ESD.................................................................. 4 KV
200A
IO L
TO OUTPUT PIN CL 50pF
+1.6V
200A
I OH
Figure 3. Load Circuit for Digital Output Timing Specifications
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch up.
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PRELIMINARY TECHNICAL DATA AD7476A/AD7477A/AD7478A
PIN CONFIGURATION AD7476A/AD7477A/AD7478A
VDD
GND
1 2 3
VIN
(Not to Scale)
AD7476A/ AD7477A/ AD7478A TOP VIEW
6 5 4
+5
SDATA
SCLK
6 Lead SC70 PIN FUNCTION DESCRIPTION
Pin Mnemonic CS VDD GND VIN SDATA
Function Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7476A/AD7477A/AD7478A and also frames the serial data transfer. Power Supply Input. The VDD range for the AD7476A/AD7477A/AD7478A is from +2.35V to +5.25V. Analog Ground. Ground reference point for all circuitry on the AD7476A/AD7477A/ AD7478A. All analog input signals should be referred to this GND voltage. Analog Input. Single-ended analog input channel. The input range is 0 to VDD. Data Out. Logic Output. The conversion result from the AD7476A/AD7477A/AD7478A is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7476A consists of four leading zeros followed by the 12 bits of conversion data which is provided MSB first. The data stream from the AD7477A consists of four leading zeros followed by the 10 bits of conversion data. The data stream from the AD7478A consists of four leading zeros followed by the 8 bits of conversion data. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7476A/AD7477A/AD7478A's conversion process.
SCLK
ORDERING GUIDE
Model AD7476AAKS AD7476ABKS AD7477AAKS AD7478AAKS EVAL-AD7476ACB 3 EVAL-AD7477ACB 3 EVAL-CONTROL BRD2 4
Temperature Range -40C -40C -40C -40C to to to to +85C +85C +85C +85C
Linearity Error (LSB)1 0.75 typ 1 max 1 max 0.5 max
Package Option2 KS-6 KS-6 KS-6 KS-6
Branding CEZ CEY CFZ CJZ
NOTES 1 Linearity Error here refers to Integral Nonlinearity. 2 KS = SC70. 3 This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demostration purposes. 4 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
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PRELIMINARY TECHNICAL DATA AD7476A/AD7477A/AD7478A
TERMINOLOGY Integral Nonlinearity Total Unadjusted Error
This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7476A and AD7477A, the endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition. For the AD7478A, the endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition.
Differential Nonlinearity
This is a comprehensive specification which includes gain error, linearity error and offset error.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. It is defined as:
THD (dB ) = 20 log V2 + V3 + V 4 + V5 + V 6 V1
2 2 2 2 2
This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
Offset Error
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonics.
Peak Harmonic or Spurious Noise
This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e, AGND + 0.5LSB. For the AD7478A, this is the desviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e, AGND + 1LSB.
Gain Error
Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak.
Intermodulation Distortion
For the AD7476A and AD7477A, this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal, i.e, VREF - 1.5LSB after the offset error has been adjusted out. For the AD7478A, this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal, i.e, VREF - 1LSB after the offset error has been adjusted out.
Track/Hold Acquisition Time
With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa - fb), while the third order terms include (2fa + fb), (2fa - fb), (fa + 2fb) and (fa - 2fb). The AD7476A/AD7477A/AD7478A are tested using the CCIF standard where two input frequencies are used (see fa and fb in the specification page). In this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs.
The track/hold amplifier returns into track mode at the end of conversion. Track/Hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 0.5 LSB, after the end of conversion. See serial interface timing section for more details.
Signal-to- (Noise + Distortion) Ratio
This is the measured ratio of signal-to-(noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal-to- (Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 12-bit converter this is 74 dB, for a 10-bit converter this is 62dB and for an 8-bit converter it is 50dB.
REV. PrE
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PRELIMINARY TECHNICAL DATA AD7476A/AD7477A/AD7478A
PERFORMANCE CURVES
Figure 4 shows a typical FFT plot for the AD7476A at 1MHz sample rate and 100kHz input frequency.
Figure 6 shows a typical FFT plot for the AD7478A at 1MHz sample rate and 100kHz input frequency.
5
-15
-35
8192PO TFFT IN VDD=2.7V Fsam =1M S p SP H Fin=100K z SIN D= 72.05dB A TH =-82.87dB D SFD =-87.24dB R
SNR - dB
TITLE
-55
TBD
-75
-95
-115 0 50 100 150 200 250 300 350 400 450 500
0
FR Q EN Y- kH EU C Z
0
TITLE
Figure 4. AD7476A Dynamic Performance at 1MSPS
Figure 6. AD7478A Dynamic Performance at 1MSPS
Figure 5 shows a typical FFT plot for the AD7477A at 1MHz sample rate and 100kHz input frequency.
Figure 7 shows the signal to (noise+distortion) ratio performance versus input frequency for various supply voltages while sampling at 1 MSPS with a SCLK frequency of 20MHz for the AD7476A.
-5 7 -5 9 -6 1 -6 3
SINAD- dB
TITLE
TBD
-6 5 -6 7 V D=4.7 5V D -6 9 -7 1 -7 3 V D=2 .7V D
V D=5 V .25 D
V D=3.6 V D V D=2.3 V 5 D
0
0
TITLE
-7 5 1 0
10 0 IN U F E U N Y- K z PT RQEC H
1 00 0
Figure 5. AD7477A Dynamic Performance at 1MSPS
Figure 7. AD7476A SINAD vs Input Frequency at 1 MSPS
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PRELIMINARY TECHNICAL DATA AD7476A/AD7477A/AD7478A
Figure 8 shows the INL performance for the AD7476A.
1 0.8 0.6 0.4 0.2 0
DNL ERROR - LSB
Figure 9 shows the DNL performance for the AD7476A.
1
V D=2.35V D Tem =250C p FSAMPL=1M P SS
VDD=2.35V Tem =250C p SP FSAMPL=1M S
0.8 0.6 0.4 0.2 0
INL ERROR - LSB
-0.2 -0.4 -0.6 -0.8 -1 0 512 1024 1536 2048 CD OE 2560 3072 3584
-0.2 -0.4 -0.6 -0.8 -1 0 512 1024 1536 2048 CD OE 2560 3072 3584
Figure 8. AD7476A INL performance.
Figure 9. AD7476A DNL performance.
CIRCUIT INFORMATION
The AD7476A/AD7477A/AD7478A are fast, micro-power, 12-/10-/8-Bit, single supply, A/D converters respectively. The parts can be operated from a +2.35V to +5.25V supply. When operated from either a 5 V supply or a 3 V supply, the AD7476A/AD7477A/AD7478A are capable of throughput rates of 1MSPS when provided with a 20MHz clock. The AD7476A/AD7477A/AD7478A provide the user with an on-chip track/hold, A/D converter, and a serial interface housed in a tiny 6-lead SC70 package, which offers the user considerable space saving advantages over alternative solutions. The serial clock input accesses data from the part but also provides the clock source for the successiveapproximation A/D converter. The analog input range is 0 to VDD . An external reference is not required for the ADC and neither is there a reference on-chip. The reference for the AD7476A/AD7477A/AD7478A is derived from the power supply and thus gives the widest dynamic input range. The AD7476A/AD7477A/AD7478A also feature a powerdown option to allow power saving between conversions. The power-down feature is implemented across the standard serial interface as described in the "Modes of Operation" section.
CONVERTER OPERATION
condition and the sampling capacitor acquires the signal on VIN.
CH AR GE RE DI ST R I B UT I ON DA C
SA MP LI NG CA P AC I TOR
CO NT RO L LO GI C
B ACQ UI SI TI ON PHAS E SW2
A
VI N
SW1
CO MPA R AT OR
AG N D
V DD / 2
Figure 10. ADC Acquisition Phase
The AD7476A/AD7477A/AD7478A is a successiveapproximation analog-to-digital converter based around a charge redistribution DAC. Figures 10 and 11 show simplified schematics of the ADC. Figure 10 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in position A, the comparator is held in a balanced
When the ADC starts a conversion, see Figure 11, SW2 will open and SW1 will move to position B causing the comparator to become unbalanced. The Control Logic and the Charge Redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced the conversion is complete. The Control Logic generates the ADC output code. Figure 12 and 13 show the ADC transfer function.
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PRELIMINARY TECHNICAL DATA AD7476A/AD7477A/AD7478A
TYPICAL CONNECTION DIAGRAM
CHARGE REDISTRIBUTION DAC
A
V IN
SAMPLING CAPACITOR
SW1 B
SW2
CONTROL LOGIC
CONVERSION PHASE
COMPARATOR
V DD / 2
AGND
Figure 11. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7476A/AD7477A/AD7478A is straight binary. For the AD7476A/AD7477A, the designed code transitions occur midway between successive integer LSB values, i.e, 0.5LSB, 1.5LSBs, etc. The LSB size is VDD/4096 for the AD7476A and VDD/1024 for the AD7477A . The ideal transfer characteristic for the AD7476A/AD7477A is shown in Figure 12. For the AD7478A, the designed code transitions occur at the succesive integer LSB values, i.e, 1LSB, 2LSBs, etc. The LSB size is in this case VDD/256. The ideal transfer characteristic for the AD7478A is shown in Figure 13.
111...111 111...110
ADC CODE
111...000
1LSB = VDD /4096 (AD7476A)
011...111
1LSB = VDD /1024 (AD7477A)
Figure 14 shows a typical connection diagram for the AD7476A/AD7477A/AD7478A. VREF is taken internally from VDD and as such VDD should be well decoupled. This provides an analog input range of 0V to VDD. For the AD7476A the conversion result is output in a 16-bit word with four leading zeros followed by the MSB of the 12-bit result. Likewise, for the AD7477A and AD7478A the conversion result consists of four leading zeros followed by the MSB of the 10-bit result and 8-bit result respectively. Alternatively, because the supply current required by the AD7476A/AD7477A/AD7478A is so low, a presision reference can be used as the supply source to the AD7476A/AD7477A/AD7478A. A REF19x voltage reference (REF195 for 5V or REF193 for 3V) can be used to supply the required voltage to the ADC - see Figure 14. This configuration is especially useful if your power supply is quite noisy or if the system supply voltages are at some value other than 5V or 3V (e.g. 15V). The REF19x will output a steady voltage to the AD7476A/AD7477A/ AD7478A. If the low dropout REF193 is used, the current it needs to supply to the AD7476A/AD7477A/AD7478A is typically 1mA. When the ADC is converting at a rate of 1MSPS the REF193 will need to supply a maximum of 1.6mA to the AD7476A/AD7477A/AD7478A. The load regulation of the REF193 is typically 10 ppm/mA (REF193, VS= 5V), which results in an error of 16ppm (48V) for the 1.6mA drawn from it. This corresponds to a 0.065 LSB error for the AD7476A with VDD= 3V from the REF193, a 0.016 LSB error for the AD7477A, and a 0.0041 LSB error for the AD7478A. For applications where power consumption is of concern, the power-down mode of the ADC and the sleep mode of the REF19x reference should be used to improve power performance. See Modes of Operation section.
+3V
000...010 000...001 000...000
0V
0.5LSB
REF193
+VDD-1.5LSB
1mA
680nF
0.1F
1F
TANT
10F
0.1F
+5V SUPPLY
ANALOG INPUT
VDD VIN
Figure 12. AD7476A/AD7477A Transfer Characteristic
0V toVDD INPUT
111...111 111...110
ADC CODE
GND
AD7476A/ AD7477A/ AD7478A
SCLK
SDATA
C/ P
&6
SERIAL INTERFACE
111...000 011...111
1LSB = V DD /256 (AD7478A)
000...010 000...001 000...000 0V
1LSB +V DD-1LSB
Figure 14. REF193 as Power Supply to AD7476A/ AD7477A/AD7478A
ANALOG INPUT
Figure 13. AD7478A Transfer Characteristic
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PRELIMINARY TECHNICAL DATA AD7476A/AD7477A/AD7478A
Table I provides some typical performance data with various references used as a VDD source with a low frequency analog input. Under the same set-up conditions the references were compared and the TBD proved the optimum reference.
Table I
Table II provides some typical performance data with various op amps used as the input buffer with a low frequency analog input. Under the same set-up conditions the op amps were compared and the TBD proved the optimum op amp.
Table II
Reference Tied AD7476A SNR Performance To VDD 1kHz Input AD780@3V REF193 AD780@2.5V REF192 AD1582
Analog Input
Op amp in the AD7476A SNR Performance input buffer 1kHz Input AD711 AD797 AD845 TBD dB TBD dB TBD dB
TBD dB TBD dB TBD dB TBD dB TBD dB
Figure 15 shows an equivalent circuit of the analog input structure of the AD7476A/AD7477A/AD7478A. The two diodes D1 and D2 provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200mV. This will cause these diodes to become forward biased and start conducting current into the substrate. 20mA is the maximum current these diodes can conduct without causing irreversable damage to the part. The capacitor C1 in Figure 15 is typically about 4pF and can primarily be attributed to pin capacitance. The resistor R1 is a lumped component made up of the on resistance of a switch. This resistor is typically about 100. The capacitor C2 is the ADC sampling capacitor and has a capacitance of 30 pF typically. For ac applications, removing high frequency components from the analog input signal is recommended by use of a bandpass filter on the relevant analog input pin. In applications where harmonic distortion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp will be a function of the particular application.
VDD
When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance will depend on the amount of total harmonic distortion (THD) that can be tolerated. The THD will increase as the source impedance increases and performance will degrade. Figure 16 shows a graph of the Total Harmonic Distortion versus Analog input frequency for different source impedances when using a supply voltage of 2.7V and sampling at a rate of 1 MSPS. Figure 17 shows a graph of the Total Harmonic Distortion versus Analog Input Signal Frequency for various supply voltages while sampling at 1 MSPS with a SCLK frequency of 20 MHz.
0 -10 -20 -30
THD - dB
V D=2.7V D
R =1 K in 0
:
-40 -50 -60 -70 -80
R =1K in
:
R =1 in 20
:
R =0 in
:
R =13 A: in
D1 C2 30 PF R1 V IN
-90 1 0 100 IN U F E U N Y- K z P T RQE C H
10 00
C1 4pF
D2 CONVERSION PHASE - SWITCH OPEN TRACK PHASE - SWITCH CLOSED
Figure 16. THD vs. Analog Input Frequency for various Source Impedance
Figure 15. Equivalent Analog Input Circuit
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PRELIMINARY TECHNICAL DATA AD7476A/AD7477A/AD7478A
The conversion is iniated on the falling edge of CS as described in the Serial Interface section. To ensure the part remains fully powered up at all times CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. If CS is brought high any time after the 10th SCLK falling edge but before the end of the tCONVERT the part will remain powered up but the conversion will be terminated and SDATA will go back into three-state. For the AD7476A sixteen serial clock cycles are required to complete the conversion and access the complete conversion result. For the AD7477A and AD7478A fourteen and twelve serial clock cycles are required to complete the conversion and access the complete conversion result, respectively.
0 0 TITLE
TITLE
TBD
Figure 17. THD vs. Analog Input Frequency, Fs = 1 MSPS
Digital Inputs
CS may idle high until the next conversion or may idle low until CS returns high sometime prior to the next conversion, (effectively idling CS low). Once a data transfer is complete (SDATA has returned to three-state), another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CS low again.
Power-Down Mode
The digital inputs applied to the AD7476A/AD7477A/ AD7478A are not limited by the maximum ratings which limit the analog inputs. Instead, the digitals inputs applied can go to 7V and are not restricted by the VDD + 0.3V limit as on the analog inputs. For example, if the AD7476A/AD7477A/AD7478A were operated with a VDD of 3V then 5V logic levels could be used on the digital inputs. However it is important to note that the data output on SDATA will still have 3V logic levels when VDD= 3V. Another advantage of SCLK and CS not being restricted by the VDD + 0.3V limit is the fact that power supply sequencing issues are avoided. If CS or SCLK are applied before VDD then there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3V was applied prior to VDD.
MODES OF OPERATION
This mode is intended for use in applications where slower throughput rates are required; either the ADC is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and then the ADC is powered down for a relatively long duration between these bursts of several conversions. When the AD7476A/AD7477A/AD7478A is in power down, all analog circuitry is powered down. To enter Power-Down, the conversion process must be interrupted by bringing CS high anywhere after the second falling edge of SCLK and before the 10th falling edge of SCLK as shown in Figure 19. Once CS has been brought high in this window of SCLKs, then the part will enter Power-Down and the conversion that was intiated by the falling edge of CS will be terminated and SDATA will go back into three-state. If CS is brought high before the second SCLK falling edge, then the part will remain in Normal Mode and will not Power-Down. This will avoid accidental Power-Down due to glitches on the CS line. In order to exit this mode of operation and power the AD7476A/AD7477A/AD7478A up again, a dummy conversion is performed. On the falling edge of CS the device will begin to power up, and will continue to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device will be fully powered up once 16 SCLKs have elapsed and valid data will result from the next conversion as shown in Figure 20. If CS is brought high before the 10th falling edge of SCLK, then the AD7476A/AD7477A/AD7478A will go back into PowerDown again. This avoids accidental power up due to glitches on the CS line or an inadvertent burst of 8 SCLK cycles while CS is low. So although the device may begin to power up on the falling edge of CS, it will power down again on the rising edge of CS as long as it occurs before the 10th SCLK falling edge.
The mode of operation of the AD7476A/AD7477A/ AD7478A is selected by controlling the (logic) state of the CS signal during a conversion. There are two possible modes of operation, Normal Mode and Power-Down Mode. The point at which CS is pulled high after the conversion has been initiated will determine whether the AD7476A/AD7477A/AD7478A will enter Power-Down Mode or not. Similarly, if already in Power-Down then CS can control whether the device will return to Normal operation or remain in Power-Down. These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements.
Normal Mode
This mode is intended for fastest throughput rate performance as the user does not have to worry about any power-up times with the AD7476A/AD7477A/AD7478A remaining fully-powered all the time. Figure 18 shows the general diagram of the operation of the AD7476A/ AD7477A/AD7478A in this mode.
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PRELIMINARY TECHNICAL DATA AD7476A/AD7477A/AD7478A
&6
SCLK
1 10
12
AD7478A AD7477A AD7476A
14
16
SDATA
VALID DATA
Figure 18. Normal Mode Operation
&6
S C LK
1
2
10
16
SD A T A
T H R E E -S T A T E
Figure 19. Entering Power Down Mode
T H E PA RT BE GIN S T O P OW ER U P
TH E PA R T I S F U L LY PO WE R ED U P W IT H V IN F UL L Y A C QU IRE D
&6
A
SCL K
1 10 16 1 16
SDA TA
INVALID D ATA
VALID DAT A
Figure 20. Exiting Power Down Mode
REV. PrE
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PRELIMINARY TECHNICAL DATA AD7476A/AD7477A/AD7478A
Power-up Time
The power-up time of the AD7476A/AD7477A/AD7478A is typically 1s, which means that with any frequency of SCLK up to 20MHz, one dummy cycle will always be sufficient to allow the device to power up. Once the dummy cycle is complete, the ADC will be fully powered up and the input signal will be acquired properly. The quite time tQUIET must still be allowed from the point where the bus goes back into three-state after the dummy conversion, to the next falling edge of CS. When running at 1MSPS throughput rate, the AD7476A/AD7477A/ AD7478A will power up and acquire a signal within +/0.5 LSB in one dummy cycle, i.e. 1s. When powering up from the Power-Down mode with a dummy cycle, as in Figure 18, the track and hold which was in hold mode while the part was powered down, returns to track mode after the first SCLK edge the part receives after the falling edge of CS. This is shown as point A in Figure 20. Although at any SCLK frequency one dummy cycle is sufficient to power the device up and acquire VIN, it does not necessarily mean that a full dummy cycle of 16 SCLKs must always elapse to power up the device and acquire VIN fully; 1s will be sufficient to power the device up and acquire the input signal. If, for example, a 5MHz SCLK frequency was applied to the ADC, the cycle time would be 3.2s. In one dummy cycle, 3.2s, the part would be powered up and VIN acquired fully. However after 1 s with a 5MHz SCLK only 5 SCLK cycles would have elapsed. At this stage, the ADC would be fully powered up and the signal acquired. So, in this case the CS can be brought high after the 10th SCLK falling edge and brought low again after a time tQUIET to initiate the conversion. When power supplies are first applied to the AD7476A/ AD7477A/AD7478A, the ADC may either power up in the Power-Down mode or in Normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. Likewise, if it is intended to keep the part in the Power-Down mode while not in use and the user wishes the part to power up in Power-Down mode, then the dummy cycle may be used to ensure the device is in power-down by executing a cycle such as that shown in Figure 19. Once supplies are applied to the AD7476A/ AD7477A/AD7478A, the power up time is the same as that when powering up from the Power-Down mode. It takes approximately 1s to power up fully if the part powers up in Normal mode. It is not necessary to wait 1 s before executing a dummy cycle to ensure the desired mode of operation. Instead, the dummy cycle can occur directly after power is supplied to the ADC. If the first valid conversion is then performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed. As mentioned earlier, when powering up from the Power-Down mode, the part will return to track upon the first SCLK edge applied after the falling edge of CS. However when the ADC powers up initially after supplies are applied, the track and hold will already be in track. This means, assuming one has the facility to monitor the ADC supply
current, if the ADC powers up in the desired mode of operation and thus a dummy cycle is not required to change mode, then neither is a dummy cycle required to place the track and hold into track.
POWER VERSUS THROUGHPUT RATE
By using the Power-Down mode on the AD7476A/ AD7477A/AD7478A when not converting, the average power consumption of the ADC decreases at lower throughput rates. Figure 21 shows how as the throughput rate is reduced, the device remains in its power-down state longer and the average power consumption over time drops accordingly. For example, if the AD7476A/AD7477A/AD7478A is operated in a continuous sampling mode with a throughput rate of 100 kSPS and a SCLK of 20MHz (VDD= 5V), and the device is placed in the Power-Down mode between conversions, then the power consumption is calculated as follows. The power dissipation during normal operation is 17.5 mW (VDD= 5V). If the power up time is one dummy cycle, i.e. 1s, and the remaining conversion time is another cycle, i.e. 1s, then the AD7476A/AD7477A/ AD7478A can be said to dissipate 17.5mW for 2s during each conversion cycle.If the throughput rate is 100 kSPS, the cycle time is 10s and the average power dissipated during each cycle is (2/10) x (17.5 mW)= 3.5 mW. If VDD= 3V, SCLK= 20MHz and the device is again in Power-Down mode between conversions, then the power dissipation during normal operation is 5.4 mW. The AD7476A/AD7477A/AD7478A can now be said to dissipate 5.4 mW for 2s during each conversion cycle. With a throughput rate of 100 kSPS, the average power dissipated during each cycle is (2/10) x (5.4 mW)= 1.08 mW. Figure 21 shows the Power vs. Throughput Rate when using the Power-Down mode between conversions with both 5V and 3V supplies. The Power-Down mode is intended for use with throughput rates of approximately 333 kSPS and under as at higher sampling rates there is no power saving made by using the power-down mode.
100
10
VDD = 5V, SCLK = 20MHz
Power (mW)
1 VDD = 3V, SCLK = 20MHz 0.1
0.01 0 50 100 150 200 250 300 350
Throughput (kSPS)
Figure 21. Power vs Throughput
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PRELIMINARY TECHNICAL DATA AD7476A/AD7477A/AD7478A
SERIAL INTERFACE
Figures 22, 23 and 24 show the detailed timing diagram for serial interfacing to the AD7476A, AD7477A and AD7478A respectively. The serial clock provides the conversion clock and also controls the transfer of information from the AD7476A/AD7477A/AD7478A during conversion. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track and hold into hold mode, takes the bus out of three-state and the analog input is sampled at this point. The conversion is also initiated at this point, for the AD7476A it will require 16 SCLK cycles to complete. Once 13 SCLK falling edges have elapsed the track and hold will go back into track on the next SCLK rising edge as shown in Figure 22 at point B. On the 16th SCLK falling edge the SDATA line will go back into three-state. If the rising edge of CS occurs before 16 SCLKs have elapsed then the conversion will be terminated and the SDATA line will go back into three-state; otherwise, SDATA returns to threestate on the 16th SCLK falling edge as shown in Figure 22. Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7476A. For the AD7477A, the 14th SCLK falling edge will cause the SDATA line to go back into three-state. If the rising edge of CS occurs before 14 SCLKs have elapsed then the conversion will be terminated and the SDATA line will go back into three-state; otherwise, SDATA returns to threestate on the 14th SCLK falling edge as shown in Figure 23. The track and hold will go back into track on the rising edge after the 13th falling, as shown in Figure 23 at
&6
tc onv e rt
point B. Fourteen serial clock cycles are required to perform the conversion process and to access data from the AD7477A. For the AD7478A, the 12th SCLK falling edge will cause the SDATA line to go back into three-state. If the rising edge of CS occurs before 12 SCLKs have elapsed then the conversion will be terminated and the SDATA line will go back into three-state; otherwise, SDATA returns to threestate on the 12th SCLK falling edge as shown in Figure 24. The track and hold will go back into track on the rising edge after the 11th falling, as shown in Figure 24 at point B. Twelve serial clock cycles are required to perform the conversion process and to access data from the AD7478A. CS going low provides the first leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges beginning with the 2nd leading zero. Thus the first falling clock edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. For the AD7476A the final bit in the data transfer is valid on the 16th falling edge, having being clocked out on the previous (15th) falling edge. In applications with a slower SCLK, it is possible to read in data on each SCLK rising edge, i.e, the first rising edge of SCLK after the CS falling edge would have the first leading zero provided and the 15th rising SCLK edge would have DB0 provided.
t1
t2
S CLK
1
2 3 4
t6
5 13
B
14
15
16
t5
t3
S DATA 3-S TATE
Z ZERO ZERO ZERO
t4
DB11
t7
DB10 DB2
DB1
t8
DB0
tquie
t
3-STATE
4 LEADING ZERO'S
1/ THROUGHPUT
Figure 22. AD7476A Serial Interface Timing Diagram
t1
&6
tc o n v er t
t2
SCLK
1
t6
2 3 4
5 13
B
14
t5
t3
SDATA 3-STATE
t4
ZE RO ZERO ZERO
t7
D B8
t8
DB0
tquiet
3 -S TATE
Z
DB9
4 LE ADI NG ZERO'S
1 / THROUGHPUT
Figure 23. AD7477A Serial Interface Timing Diagram
REV. PrE
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PRELIMINARY TECHNICAL DATA AD7476A/AD7477A/AD7478A
t1
&6
tconvert
t2
SCLK
t6
1
2 3 4
B
5 11
12
t5
t3
SDATA 3-STATE
Z ZE RO ZE RO ZERO
t4
DB7
4 LEADI NG ZERO'S
t7
DB6
t8
DB0
tquiet
3 -S TATE
1/ THRO UG HP UT
Figure 24. AD7478A Serial Interface Timing Diagram
MICROPROCESSOR INTERFACING
The serial interface on the AD7476A/AD7477A/AD7478A allows the part to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7476A/AD7477A/AD7478A with some of the more common microcontroller and DSP serial interface protocols.
AD7476A/AD7477A/AD7478A to TMS320C541 Interface
The connection diagram is shown in Figure 25. It should be noted that for signal processing applications, it is imperative that the frame synchronisation signal from the TMS320C541 will provide equidistant sampling.
The serial interface on the TMS320C541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7476A/AD7477A/AD7478A. The CS input allows easy interfacing between the TMS320C541 and the AD7476A/AD7477A/AD7478A without any glue logic required. The serial port of the TMS320C541 is set up to operate in burst mode (FSM=1 in the Serial Port Control register, SPC) with internal serial clock CLKX (MCM=1 in SPC register) and internal frame signal (TXM=1 in the SPC), so both pins are configured as an outputs. For the AD7476A the word length should be set to 16 bits (FO=0 in the SPC register). This DSP only allows frames with a word length of 16 or 8 bits. Therefore, in the case of the AD7477A and AD7478A where 14 and 12 bits would be required, the FO bit will be set up to 16 bits also. This means to obtain the conversion result 16 SCLKs will be needed. In both situations, the remaining SCLKs will clock out trailing zeros. For the AD7477A two trailing zeros will be clocked out in the two last clock cycles, for the AD7478A 4 trailing zeros will be clocked out. To summarise, the values in the SPC register are: FO=0 FSM=1 MCM=1 TXM=1 The format bit, FO, may be set to 1 to set the word length to 8-bits, in order to implement the Power-Down mode on the AD7476A/AD7477A/AD7478A.
AD7476A/ AD7477A AD7478A*
TMS320C541*
SCLK CLKX CLKR SDATA DR FSX FSR
&6
*Additional Pins omitted for clarity
Figure 25. Interfacing to the TMS320C541
AD7476A/AD7477A/AD7478A to ADSP218x
The ADSP218x family of DSPs are interfaced directly to the AD7476A/AD7477A/AD7478A without any glue logic required. The SPORT control register should be set up as follows: TFSW= RFSW= 1, Alternate Framing INVRFS= INVTFS= 1, Active Low Frame Signal DTYPE= 00, Right Justify Data ISCLK= 1, Internal Serial Clock TFSR= RFSR= 1, Frame Every Word IRFS= 0, it sets up RFS as an Input ITFS= 1, it sets up TFS as an Output SLEN= 1111, 16 bits for the AD7476A SLEN= 1101, 14 bits for the AD7477A SLEN= 1011, 12 bits for the AD7478A To implement the Power-Down mode SLEN should be set to 1001 to issue an 8-bit SCLK burst. The connection diagram is shown in Figure 26. The ADSP218x has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates
REV. PrE
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PRELIMINARY TECHNICAL DATA AD7476A/AD7477A/AD7478A
in Alternate Framing Mode and the SPORT control register is set up as described. The frame synchronisation signal generated on the TFS is tied to CS and as with all signal processing applications equidistant sampling is necessary. However, in this example, the timer interrupt is used to control the sampling rate of the ADC and, under certain conditions, equidistant sampling may not be achieved. The timer registers etc., are loaded with a value which will provide an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and hence the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given, i.e. AX0= TX0, the state of the SCLK is checked. The DSP will wait until the SCLK has gone high, low and high before transmission will start. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, the data may be transmitted or it may wait until the next clock edge. For example, the ADSP2111 has a master clock frequency of 16MHz. If the SCLKDIV register is loaded with the value 3 then a SCLK of 2MHz is obtained, and 8 master clock periods will elapse for every one SCLK period. If the timer registers are loaded with the value 803, 100.5 SCLKs will occur between interrupts and subsequently between transmit instructions. This situation will result in non-equidistant sampling as the transmit instruction is occuring on a SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N then equidistant sampling will be implemented by the DSP.
AD7476A/ AD7477A AD7478A*
ADSP218x*
SCLK
SDATA
the option for a 14 bits word length, so the AD7477A word length will be set up to 16 bits like the AD7476A. For the AD7477A the conversion process will use 16 SCLKs cycles, with the last two clock periods clocking out two trailing zeros to fill the 16 bits word. To implement the Power-Down mode on the AD7476A/ AD7477A/AD7478A, the word length can be changed to 8 bits by setting bits WL2=0, WL1=0 and WL0=0 in CRA. The FSP bit in the CRB register can be set to 1, that means that the frame goes low and a conversion starts. Likewise, by means of the bits SCD2, SCKD and SHFD in the CRB register, it will be established that the pin SC2 (the frame sync signal) and SCK in the serial port will be configured as outputs and the MSB will be shifted first. To sum up, MOD=0 SYN=1 WL2, WL1, WL0 depend on the word length FSL1=1, FSL0=0 FSP=1, negative frame sync SCD2=1 SCKD=1 SHFD=0 It should be noted that for signal processing applications, it is imperative that the frame synchronisation signal from the DSP563xx will provide equidistant sampling.
AD7476A/ AD7477A AD7478A*
DSP563xx*
SCLK
SCK SRD SC2
SDATA
&6
*Additional Pins omitted for clarity
SCLK
DR RFS TFS
&6
Figure 27. Interfacing to the DSP563xx
*Additional Pins omitted for clarity
Figure 26. Interfacing to the ADSP-218x
AD7476A/AD7477A/AD7478A to DSP563xx Interface
The connection diagram in Figure 27 shows how the AD7476A/AD7477A/AD7478A can be connected to the SSI (Synchronous Serial Interface) of the DSP563xx family of DSPs from Motorola. The SSI is operated in Synchronous and Normal Mode (SYN=1 and MOD=0 in the Control Register B, CRB) with internally generated 1bit clock period frame sync for both Tx and Rx (bits FSL1=1 and FSL0=0 in the CRB). Set the word length in the Control Register A (CRA) to 16 by setting bits WL2=0, WL1=1 and WL0=0 for the AD7476A. The word length for the AD7478A will be set to 12 bits (WL2=0, WL1=0 and WL0=1). This DSP does not offer REV. PrE -19-
PRELIMINARY TECHNICAL DATA AD7476A/AD7477A/AD7478A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
6-Lead SC70 (KS)
0.087 (2.20) 0.071 (1.80)
0.053 (1.35) 0.045 (1.15)
6
5
4
0.094 (2.40) 0.071 (1.80)
1
2
3
PIN 1 0.026 (0.65) BSC 0.051 (1.30) BSC 0.039 (1.00) 0.031 (0.80) 0.012 (0.30) 0.006 (0.15) 0.043 (1.10) 0.031 (0.80) 8o 0o
0.004 (0.10) 0.000 (0.00)
SEATING PLANE
0.007 (0.18) 0.004 (0.10)
0.012 (0.30) 0.004 (0.10)
-20-
REV. PrE

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